1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of testing the same, and more particularly, to a semiconductor memory device in which a test circuit for an operation/function test is integrated and a method of testing the same.
Priority is claimed on Japanese Patent Application No. 2010-000467, Jan. 5, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
In semiconductor memory devices such as DRAMs, data is input/output in parallel by a number of input/output terminals. When data is input to some input/output terminals, an unused input/output terminal is masked to prevent data from being input to the unused input/output terminal. In particular, a write mask operation is known, in which specific bits are not written during a write operation. Japanese Unexamined Patent Application, First Publication No. JP-A-2007-80515 discloses the write mask operation. In the write mask operation, data is prevented from being written to a memory cell by deactivating a write amplifier and a sub-amplifier connected to an input/output terminal which has received no input of data.
FIG. 5 is a diagram illustrating a schematic configuration from a write amplifier, which amplifies data to be written, to a pair of bit lines BL and /BL. When the write mask operation is performed, a write amplifier 121A is deactivated and its output is in a high impedance state. A sub-amplifier SUB is also deactivated. The sub-amplifier is connected to local input/output lines LIO (local I/O lines) branched from main input/output lines MIO (main I/O lines). However, an operation other than those of the write amplifier 121A and the sub-amplifier SUB is the same as a normal data write operation. That is, a Y switch YS and a write switch WS are placed in conductive state, and a sense amplifier SA is also activated. Accordingly, the sense amplifier SA amplifies data on the bit lines BL and /BL, the data having been read out of selected memory cells (not shown). However, the local input/output line LIO and the main input/output line MIO are also connected to the bit line BL. That is, the sense amplifier SA needs to drive the local input/output line LIO and the main input/output line MIO in accordance with a potential of the bit line BL. When the normal write operation, not the write mask operation, is performed, the potential of the bit line BL is determined by the write amplifier 121 in accordance with data to be written. The data is written to a selected memory cell.
When the write mask operation is performed, the main input/output line MIO and the local input/output line LIO as well as the bit line BL are connected to the sense amplifier SA. Hence, a load is maximized for the sense amplifier SA. Thus, if the load driving capability of the sense amplifier SA is less than a predetermined capability due to the variation of a fabrication process or the like, it is impossible to amplify data of the selected memory cell appearing on the bit line BL without any error.
In a screening process after assembly, a write mask operation test is also performed. A semiconductor memory device in which a defective sense amplifier SA is formed (that is, load driving capability of the sense amplifier SA is low) is detected as a defective product.